INTRODUCTION TO LOGIC CIRCUITS & LOGIC DESIGN WITH VERILOG

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dc.contributor.authorLaMeres, Brock
dc.contributor.programINGENIERÍA INDUSTRIALen_US
dc.coverageSuizaen_US
dc.date.accessioned2020-05-12T19:59:37Z
dc.date.available2020-05-12T19:59:37Z
dc.date.issued2019
dc.format.extent485en_US
dc.format.mediumDIGITALen_US
dc.format.mimetypePDFen_US
dc.identifier.citationLameres, B. (2019). INTRODUCTION TO LOGIC CIRCUITS & LOGIC DESIGN WITH VERILOG. Suiza: Springer.en_US
dc.identifier.urihttps://dspace-uh-tmp.igniteonline.la/handle/cenit/5905
dc.language.isoenen_US
dc.publisherSpringeren_US
dc.titleINTRODUCTION TO LOGIC CIRCUITS & LOGIC DESIGN WITH VERILOGen_US
dc.typeBooken_US

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